Semantic Validation of VHDL-AMS by an Abstract State Machine
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چکیده
This report presents a semantic analysis for VHDL-AMS, a mixed-signal extension of VHDL, based on an abstract state machine. Intended as a validation for the on-going standardization project, it faithfully reflects the view of simulation proposed. Our experiences proved practical advantages of formal approach in sharing concepts.
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تاریخ انتشار 1997